Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens;” however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens.” Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). One technique, which is currently receiving attention from the photolithography community, for further improving the resolution/printing capabilities of photolithography equipment is referred to as chromeless phase lithography “CPL”. As is known, when utilizing CPL techniques, the resulting mask pattern typically includes structures (corresponding to features to be printed on the wafer) which do not require the use of chrome (i.e., the features are printed by phase-shift techniques) as well as those that utilize chrome. Such CPL masks have been disclosed in USP Publication No. 2004-0115539 (the '539 reference), which is herein incorporated by reference in its entirety.
As discussed in the '539 reference, for actual manufacturing purposes it was found that it was beneficial to classify the mask design features into “three zones”. Referring to FIG. 1a, Zone 1 features are those features with a critical dimension in the range that two phase edges (left and right) interact closely and form a single aerial image. As the two phase edges become further apart (or larger feature CD), each of the left and right phase edge form its own aerial image and the two do not interact, as shown in FIG. 1c. This type of feature is classified as a Zone 3. In this case, in order to prevent the Zone 3 features from being printed as two separate line patterns, a piece of dark chrome is placed on the top of the substrate, and the Zone 3 feature forms a single aerial image as shown in FIG. 1c. In other words, the Zone 3 features essentially become “chrome” mask features.
In the case where the CD dimension is such that the two phase-edges partially interact as shown in FIG. 1b, these features are classified as Zone 2 features. However, the aerial images formed by the partial phase edge interaction are quite poor in quality, and therefore unusable. The '539 reference discloses that by tuning the percent transmission using chrome patches, it is possible to obtain high fidelity aerial image for such features. Accordingly, by classifying the randomly designed mask features into the three imaging zones, and then applying optical proximity correction (OPC) accordingly, it is possible to achieve volume IC manufacturing with a CPL mask.
FIGS. 2a and 2b illustrate the application of the chrome patches (referred to as the “zebra” technique) and the application of a standard alternating phase-shift mask (Alt-PSM), respectively, for Zone 2 features, as well as a comparison between the performance of the CPL zebra technique and the Alt-PSM technique. Referring to FIG. 2a, for Zone 2 features (which in the given example are three parallel lines), the quartz substrate 20 is etched so as to form three sets of adjacent π-phase edges and then chrome patches 22 are disposed on top of the features 24 formed by the etching so as to form strips/patches of chrome (i.e., zebra pattern) on the upper surface of the etched feature 24. The duty ratio of the “zebra” pattern needs to be un-resolvable by the imaging tool so that the “zebra” essentially become digitally halftoned. In other words, the Zone 2 features are “shaded” phase patterns from the image tool point of view. The amount of shade (i.e., percentage transmission) is determined by the ratio between the size of the chrome patches (dark) vs. the size of the open areas (clear). By utilizing these patches, it is possible to control the percentage transmission for the Zone 2 mask features, and achieve high fidelity patterning.
Indeed, as shown in FIG. 2a, the “zebra’ features comfortably rival the imaging performance associated with a standard alternating PSM (AltPSM) mask 26, which is illustrated in FIG. 2b, and is imaging the same three parallel line pattern as imaged by the mask in FIG. 2a. As shown, both of the resulting aerial images show excellent minimum aerial image (I-min), and better image contrast since lower I-min means it is a “darker” image that can better form a higher fidelity line pattern. However, for the Zone 2 features imaged utilizing the zebra CPL technique, the resulting aerial image is inherently much more symmetrical near the outer sides of the group line patterns. This is one of the major benefits of using the zebra CPL techniques because a more practicable OPC treatment is feasible. One issue with utilizing the zebra technique for implementing Zone 2 features in a mask is that such zebra mask features require the use of an e-beam or high-resolution mask making process. Borderline quality zebra mask patterns reduce effectiveness of transmission control during patterning. The zebra pattern can also cause difficulty in reticle inspection that is necessary to ensure defect free masks. However, it is noted that for the leading edge lithography manufacturing, zebra features are the best option if a quality CPL zebra mask is deliverable.
In view of the foregoing, it is therefore desirable to have a CPL mask that can minimize the use of zebra patterns for imaging Zone 2 features, but which can still achieve the satisfactorily printing performance. Moreover, due to the variety of IC design styles, such as memory core vs. periphery pattern area, it is desirable to have a more flexible and improved CPL mask design that satisfies the printing performance required without necessarily resorting to the use of the zebra mask design for imaging, for example, Zone 2 features.
Thus, it is an object of the present invention to provide an alternative to the zebra patterning technique previously disclosed in the '539 reference, so as to provide a CPL mask which eliminates the foregoing issues associated with utilizing the zebra patterning technique.